1. Field of the Invention
The present invention relates to a demodulation method wherein clock synchronization is established from a burst signal which is modulated by means of the π/4-shift QPSK (Quadrature Phase Shift Keying) modulation scheme, for example, to a synchronization establishment apparatus, modem or base station, and particularly to a technique for establishing synchronization in a short period of time.
2. Description of the Prior Art
In a wireless communications system wherein wireless communication is performed in a burst manner, a wireless transmitter wirelessly transmits a burst signal which is modulated by a modulator, and at the time that a wireless receiver begins the receipt of the burst signal, the establishment of clock synchronization from the burst signal is performed by a demodulator In addition, in such a wireless communications system, various modulation schemes and demodulation schemes are used, for example, π/4-shift QPSK.
FIG. 16 shows one example of the structure of a burst signal.
As shown in FIG. 16, the various burst slots contained within a burst signal consist of, in order from the beginning, a preamble pattern (PR) which is a pattern for establishing synchronization, a unique word (UW) which is an identification pattern for determining the base position of the burst, DATA which is the body of communications data, and guard bits (GB) which prevent the overlapping of bursts by providing buffer timing between slots.
When communication is performed in bursts, the receiver refers to the preamble pattern at the start of receiving the respective bursts, and establishes the synchronization of its own clock. When a burst signal having a frame format as shown in FIG. 16 above is used, it is preferable to establish synchronization prior to the unique word, for example.
In addition, FIG. 17 shows one example of a demodulation circuit which is implemented in a wireless receiver that establishes clock synchronization as described above. In this demodulation circuit, clock synchronization is established by means of feedback control as a typical method. In addition, the example shown in FIG. 17 illustrates the case in which demodulation is performed by the delay detection system wherein π/4-shift QPSK is used as the modulation scheme.
Specifically, in the demodulation circuit illustrated in FIG. 17, a (π/4-shift QPSK) burst signal received by a wireless receiver is converted from an analog signal to a digital signal by means of an A/D converter 81, demodulated into an I component (in-phase component) and a Q component (quadrature component) by a demodulator 82, and then the I component and the Q component are filtered by filter 83 and filter 84, respectively.
The I component and the Q component which are output from the two filters 83 and 84 are input to a (delayed) detector 85 and are also input to a clock phase detection circuit 86. Moreover, in the detector 85, the input I component and the Q component are demodulated by delayed detection so as to generate demodulated data. In addition, a parallel/serial converter 88 converts the demodulated data of the I component and the Q component output from the detector 85 from parallel data to serial data. Further, the clock phase detection circuit 86 detects the phase of the clock from the inputted I component and Q component, and a clock regeneration circuit 87 generates a synchronization clock based on the results of this detection, whereby feedback control of the aforementioned A/D converter 81, filters 83 and 84, and detector 85 is performed.
As an example of the prior art of π/4-shift QPSK synchronization detection circuits, we shall describe the “Digital Demodulation Circuit, Maximum Value Detection Circuit and Receiver” recited in the publication of unexamined Japanese patent application JP-A-9-266499.
This example of prior art relates to a Personal Handy phone System (PHS) or other mobile communications system, with an object of providing a digital demodulator having a synchronization detection circuit that enables a high-speed operation and that can be implemented in a more compact manner or in ICs, and relates to technology for eliminating frequency errors and phase errors between the transmitter and receiver.
Specifically, in this prior-art example, a preamble pattern consisting of a repeated pattern of “1001” is used, and by detecting the frequency difference during the period of this preamble pattern and by forming a frequency difference compensation signal based on a phase change pattern of instantaneous phase signals during this preamble pattern, it is intended to enlarge the permissible range of phase noise over which the phase difference between the carrier signals can be correctly detected
In addition, in this prior-art example, a carrier generator compares the phase of the carrier signal it generates itself against the phase of the carrier signal of the received signal so as to detect the phase error, and thus the establishment of synchronization is performed by correcting this phase error. In addition, in this prior-art example, the phase of the π/4-shift QPSK received signal is shifted backwards by π/4 and processing is performed in a manner corresponding to QPSK. In this case, the preamble pattern becomes a waveform wherein a phase change of π is repeated every symbol, so it can be treated as a Binary Phase Shift Keying (BPSK) signal, and thus it is resistant to erroneous detection due to phase noise and high-precision phase detection is possible.
However, in the prior-art demodulation circuit shown in FIG. 17, in order to establish clock synchronization based on the preamble pattern, with the performance of a typical receiver, there is a difficulty in that a reception period is required that is as long as approximately 100 symbols from the start of reception of the burst signal.
Here, with reference to FIG. 18, we shall describe in detail the problems that occur due to the aforementioned difficulty.
FIG. 18(a) shows an example of the structure of a burst signal in the case wherein, in order to handle the long period until the establishment of the clock of approximately 100 symbols, a preamble pattern having a length (period) which is equivalent to 100 symbols or longer is provided. However, in this case, since the length (period) of the preamble pattern becomes a large fraction of the length (period) of the entire burst slot, there is a problem in that this preamble pattern period becomes wasted time in data communications, thus decreasing the data communications (transmission) rate.
In addition, FIG. 18(b) shows an example of the structure of a burst signal in the case wherein the length (period) of the preamble pattern is not as long as that shown in FIG. 18(a). In this case, there is a possibility that the received signal cannot be demodulated correctly during the period of roughly 100 symbols from the start of reception, so there is a possibility that at the time of reception of the first burst, the unique word and data periods also cannot be demodulated normally. For this reason, there is the problem in that it will be assumed that the data received during the receipt of the first burst cannot be received normally and thus this data received in the first burst will be discarded. In addition, there is also a problem in that the timing of synchronization which is established at the time of receipt of the first burst must be stored for use at the time of receipt of the second and subsequent bursts.
The present invention was accomplished in order to solve the aforementioned problems with the prior art. Accordingly, an object of the present invention is to provide a demodulation method wherein, at the time of the establishment of clock synchronization based on a burst pattern contained at the front of a (π/4-shift QPSK) burst signal, synchronization can be established in a short period of time, and also to provide a synchronization establishment apparatus, modem and base station.